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IEEE Transactions on Computers

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writing FSM in verilog differen

       

 

       

 
      What are the cases in which metastability occurs?  

As we have seen that whenever setup and hold violation time occurs, metastability occurs, so we have to see when signals violate this timing requirement:

 
       

 

When the input signal is an asynchronous signal.

When the clock skew/slew is too much (rise and fall time are more than the tolerable values).

When interfacing two domains operating at two different frequencies or at the same frequency but with different phase.

When the combinational delay is such that flip-flop data input changes in the critical window (setup+hold window)

 
       

 
      What is MTBF?  

MTBF is Mean time between failure, what does that mean? Well MTBF gives us information on how often a particular element will fail or in other words, it gives the average time interval between two successive failures. The figure below shows a typical MTBF of a flip-flop and also it gives the MTBF equation. I am not looking here to derive MTBF equation :-)

 
       

 

../images/tidbits/meta.h2.gif

         

 
      So how do I avoid metastability?  

In reality, one cannot avoid metastability and increased clock-to-Q delays in synchronizing asynchronous inputs, without the use of tricky self-timed circuits. So a more appropriate question might be "How do I tolerate metastability?"

 
       

 

In the simplest case, designers can tolerate metastability by making sure the clock period is long enough to allow for the resolution of quasi-stable states and for the delay of whatever logic may be in the path to the next flip-flop. This approach, while simple, is rarely practical given the performance requirements of most modern designs.

 
       

 

The most common way to tolerate metastability is to add one or more successive synchronizing flip-flops to the synchronizer. This approach allows for an entire clock period (except for the setup time of the second flip-flop) for metastable events in the first synchronizing flip-flop to resolve themselves. This does, however, increase the latency in the synchronous logic's observation of input changes.

 
       

 

Neither of these approaches can guarantee that metastability cannot pass through the synchronizer; they simply reduce the probability to practical levels.

 
       

 

In quantitative terms, if the Mean Time Between Failure (MTBF) of a particular flip-flop in the context of a given clock rate and input transition rate is 33.33 seconds then the MTBF of two such flip-flops used to synchronize the input would be (33.33* 33.33) = 18.514 Minutes. Well I have taken the worst flip-flop ever designed in history of man kind :-). The figure below shows how to connect two flip-flops in series to achieve this and also the resultant MTBF.

 
       

 

../images/tidbits/meta.h1.gif

         

 

Normally,

 
       

 

We can use a metastable hardened flip-flop

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